总线这个概念有点复杂. 总线可以被N多device共同使用, 各种device均并联在这条总线上，但是在任一时刻, 总线只有一个device在使用. 就就像电话机一样只有拨通各自的号码才能工作，所以每个电路和模块都有唯一的地址.
关于总线的概念, 比较偏向于硬件设计, 所以看下面的文章也看不出什么头绪:
http://en.wikipedia.org/wiki/Bus_(computing)
North bridge: 北桥, The northbridge, also known as a memory controller hub (MCH) or an integrated memory controller (IMC) 关于总线的概念, 比较偏向于硬件设计, 所以看下面的文章也看不出什么头绪:
http://en.wikipedia.org/wiki/Bus_(computing)
1. 前端总线
CPU与北桥相连的总线称为前端总线(FSB), 它影响到CPU访问memory的速度2. 南桥与北桥
典型PC机的CPU与其它硬件的连接图:CPU与其它硬件通信都要通过北桥. 北桥管理南桥, memory, Graphics card
South bridge: 南桥, The Southbridge, also known as an I/O Controller Hub (ICH) or a Platform Controller Hub (PCH)
南桥主要管理I/O硬件, 这类硬件的速度都较低
3. PCI总线
PCI全称为Peripheral Component Interconnect. 也为一种总线, 它的设计目的:The purpose of the PCI local bus standard is to provide a means of
transferring data between devices in a computer.
4. 高速I/O总线PCI-E
PCI这种并行总线设计上存在的极限速度, 这样外设(peripherals)就有速度上的限制. 对于高速的I/O设备呢?如: Gigabit网卡, SATA, SAS
I/O的速度需求, 也给北桥与南桥之间的总线带来压力:
Link Between Northbridge and Southbridge.
Congestion on the PCI bus also affects the link between the Northbridge
and the Southbridge. SATA drives and USB devices further stress this
link. A higher-bandwidth link will be required in the future.
Congestion on the PCI bus also affects the link between the Northbridge
and the Southbridge. SATA drives and USB devices further stress this
link. A higher-bandwidth link will be required in the future.
因些, 出现PCI-Express. 速度为 5-80 gigabits per second (Gbps), PCI-E为串行型总线
PCI-E与PCI的兼容情况
PCI Express provides a scalable, high-speed, serial
I/O bus that maintains backward compatibility with PCI applications and
drivers. The PCI Express layered architecture supports existing PCI
applications and drivers by maintaining compatibility with the existing
PCI load-store (and flat address space) model.
I/O bus that maintains backward compatibility with PCI applications and
drivers. The PCI Express layered architecture supports existing PCI
applications and drivers by maintaining compatibility with the existing
PCI load-store (and flat address space) model.
PCI-Express被用于高速设备之间的连接, 如下为现在的PC设计:
1. PCI-Express取代AGP总线
2. 北桥与南桥使用PCI-Express variant替代
3. Gigabit型网卡与PCI-Express相连
4. PCI还是被保留
便携式电脑有自己的硬件结构:
从上面的文字: Devices Integrated on system board, 看出主板上的集成设备使用PCI-E总线
USB2.0设备没有被挂到PCI-E总线上! 而是直接与南桥连接
1. PCI-Express取代AGP总线
2. 北桥与南桥使用PCI-Express variant替代
3. Gigabit型网卡与PCI-Express相连
4. PCI还是被保留
便携式电脑有自己的硬件结构:
从上面的文字: Devices Integrated on system board, 看出主板上的集成设备使用PCI-E总线
USB2.0设备没有被挂到PCI-E总线上! 而是直接与南桥连接
* 这里有计算机总线技术变迁, 这有意思的变化: http://www.dell.com/content/topics/global.aspx/vectors/en/2004_pciexpress?c=us&l=en
5. 其它总线
PC机还有其它总线, 这些总线都bridge转换后连接到PCI总线上. 如: ISA-PCI bridge6. 硬件探测
我的机器都有哪些硬件? 硬件的探测工具:* http://www.gentoo-wiki.info/Detecting_your_Hardware
对于硬件的探测工具, 有个有意思的问题:
探测有两种:
1. 直接探测硬件, directly probe the raw hardware
2. 从kernel中收集硬件信息, retrieve the information from kernel
这下是搜出的关于这种问题的讨论:
* http://www.vlug.org/pipermail/discuss/2006-March/020875.html
一个叫David Bronaugh的说:
So neither of these utilities "directly talk with the raw hardware".
They use the kernel as an intermediary, as they should. You're not going
to find many programs in linux (other than the X.org X window system)
that talk directly to hardware without some kind of kernel arbitration,
because it's dangerous.
kernel的安全机制不给directly probe hardwareThey use the kernel as an intermediary, as they should. You're not going
to find many programs in linux (other than the X.org X window system)
that talk directly to hardware without some kind of kernel arbitration,
because it's dangerous.
还有一个 J.Bakshi 的指出lspci三个有意思的参数: -H1, -H2, -M. 如下是lspci的-H1文档:
-H1 Use direct hardware access via Intel configuration mechanism 1.
看来不是随意就可以talk directly to hardware的!
